6-2 A 2-GHz Direct Sampling Delta-Sigma Tunable Receiver with 40-GHz Sampling Clock and On-chip PLL
نویسندگان
چکیده
This paper presents a 2-GHz tunable direct sampling receiver with 40-GHz sampling clock and on-chip PLL, fabricated in a production 130-nm SiGe BiCMOS process. The measured SFDR and SNDR are 59 dB and 59.84 dB, respectively, over a bandwidth of 60 MHz, and the effective number of bits (ENOB) equals 9.65. Compared to the case where an external low-noise 40-GHz clock was used, no SNDR degradation was observed when the on-chip VCO and PLL were employed. The entire receiver with PLL occupies an area of 1.58x2.39 mm and consumes 2.19 W when powered from a 2.5-V supply.
منابع مشابه
Design and VLSI Implementation of Second Order Sigma-Delta Modulation ADC for I-UWB Receiver
Analog to Digital converters plays an essential role in modern mixed signal circuit design. Mixed-signal System-on-chip devices such as Analog-to-Digital Converters (ADC) have become increasingly prevalent in the semiconductor industry. Nyquist Samplers require a complicated analog low pass filter to limit the maximum frequency input to the A/D and Sample and Hold circuit. Sigma-Delta (ΣΔ) modu...
متن کاملA superconducting bandpass delta-sigma modulator for direct analog-to-digital conversion of microwave radio
Direct analog-to-digital conversion of multi-GHz radio frequency (RF) signals is the ultimate goal in software radio receiver design but remains a daunting challenge for any technology. This thesis examines the potential of superconducting technology for realizing RF analogto-digital converters (ADCs) with improved performance. A bandpass delta-sigma (∆Σ) modulator is an attractive architecture...
متن کاملAN ABSTRACT OF THE DISSERTATION OF Karthikeyan Reddy for the degree of Doctor of Philosophy in Electrical and Computer Engineering presented on March 10, 2014. Title: Design Techniques For Delta Sigma Modulators Using VCO Based ADCs
approved: Pavan Kumar Hanumolu VCO-based ADCs have recently emerged as attractive alternative to conven tional Delta Sigma (ΔΣ) modulator architectures. Few salient features of a VCO based ADC are: 1) the quantization noise is 1 order noise shaped, 2) it is an open loop architecture, and, 3) its implementation is mostly digital in nature. Hence, they are ideally suited for oversampled data co...
متن کاملDesign and Implementation of a Low Power Second Order Sigma-Delta ADC
Sigma-Delta (∑-∆) analog to digital converters are well known for its use in high accuracy wireless communication applications. It is alternative for low power, high resolution (greater than 12 bits) converters, which can be ultimately integrated on digital signal Processor ICs. In this work Over Sampling concept is used to address the problem of power dissipation and noise in ADCs. In this pap...
متن کاملA 0.8-2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling Bandpass ΣΔ ADC in 0.13 µm CMOS
A reconfigurable bandpass continuous-time RF ADC tunable over the 0.8–2 GHz frequency range is presented. Systemand circuit-level innovations provide low power consumption and reduced circuit complexity. The proposed architecture operates in both the firstand second-Nyquist zones to enable a wide tuning range from a fixed sampling frequency of 3.2 GHz. A fully-integrated on-chip quadrature phas...
متن کامل